-Secondary Cache and System Interface Timing

12.2 AC Electrical Specification

Secondary Cache and System Interface Timing

Timing measurements are referenced from the mid-swing point of the input signal to the crossing point of the SysClk and SysClk* input clocks. All input signals maintain a 1 V/ns edge rate in the 20% to 80% range of the input signal swing.

Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96

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